Job Description and Responsibilities:
As a senior technical lead engineer, you will propose and evaluate new architectural proposals for next generation FPGAs. You will lead the design and development of critical digital circuit blocks in the chip. Architectural enhancements, circuit optimizations and process technology advancements will be applied by you to the blocks as required by design specifications. You will be a technical leader.
Job responsibilities will include but not limited to:
• Digital circuit design of dual port SRAM including Self-timed circuits and Sense amplifiers
• State machine and LUT based circuit design
• Using CAD tools extensively to simulate circuit performance and validation.
• Verifying and characterizing the circuit behavior on silicon.
• Being the main technical reference resource for the entire team
Qualifications include a MSEE or equivalent with minimum 8 years direct related experience in IC Design and have several successful product tapeouts. Other qualifications include:
• Power management design experience.
• Expert in HSPICE/HSIM/ Power analysis tools.
• Expert in shell/PERL and other scripting tools.
• Effective communication skills
ravikir@xilinx.com
Thursday, November 5, 2009
Wednesday, November 4, 2009
Analog Circuit Design - PLL Lead to work for Xilinx highend products
Title: Senior Technical Lead Engineer - Analog PLL Ckt. Design
Job Description and Responsibilities:
As a senior technical lead engineer, you will propose and evaluate new architectural proposals for Clock distribution and Clock management circuits in next generation FPGAs. You will lead the design and development of critical analog circuit blocks in the chip. Architectural enhancements, circuit optimizations and process technology advancements will be applied by you to the blocks as required by design specifications. You will be a technical leader.
Job responsibilities will include but not limited to:
- Analog circuit design of PLL, in-particular the VCO and power regulators
- Analog circuit design of high-speed IO buffers
- System level analysis of Clocking, SERDES/DPA and link performance.
- Using CAD tools extensively to simulate circuit performance and validation.
- Verifying and characterizing the circuit behavior on silicon.
- Being the main technical reference resource for the entire team
Qualifications include a MSEE or equivalent with minimum 8 years direct related experience in IC Design and have several successful product tapeouts. Other qualifications include:
- Signal Integrity analysis and experience.
- Expert in HSPICE/HSIM/ Power analysis tools.
- Expert in shell/PERL and other scripting tools.
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